Zeng, Haoran; Feng, Yingqi; Li, Tianai; Ye, Hang; Huang, Zunkai; Wang, Hui; Tian, Li; Zhu, Yongxin; Li, Qiliang; Ha, Yajun

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

2025, ,

Zeng, Haoran; Feng, Yingqi; Li, Tianai; Ye, Hang; Huang, Zunkai; Wang, Hui; Tian, Li; Zhu, Yongxin; Li, Qiliang; Ha, Yajun

Achieving high power efficiency in Mobile Industry Processor Interface (MIPI) D-PHY receivers is crucial for micro-display chips in AR/VR systems, where stringent power constraints exist. However, existing designs often sacrifice power efficiency for higher data rates due to architectural limitations, neglecting optimization for low-power applications. To address this issue, we propose a receiver architecture that substantially enhances power efficiency through three key techniques. First, we improve the gain-bandwidth product (GBW) by employing an autonomous gain scheduling analog front-end (AFE) that dynamically tunes the gain while reducing drive current. Second, we reduce clocking overhead by introducing a self-monitoring interferometric deserializer that enables clock-free pre-scaling and halves the DDR sampling frequency. Third, we increase transition speed and minimize short-circuit power by utilizing a chaotic topological flow actuator (CTFA) with multi-path current feedthrough. Compared to prior state-of-the-art designs, the proposed receiver achieves a power efficiency of 50 mu W/Gbps/lane (42 mu A/Gbps/lane), reducing power and current consumption by 46% and 45%, respectively, using a standard 180-nm process.